Low Complexity, High Speed VLSI Architectures for Error Correction Decoders
| Author | : Yanni Chen |
| Publisher | : |
| Total Pages | : 294 |
| Release | : 2003 |
| ISBN-10 | : MINN:31951P00831754L |
| ISBN-13 | : |
| Rating | : 4/5 ( Downloads) |
Book Synopsis Low Complexity, High Speed VLSI Architectures for Error Correction Decoders by : Yanni Chen
Download or read book Low Complexity, High Speed VLSI Architectures for Error Correction Decoders written by Yanni Chen and published by . This book was released on 2003 with total page 294 pages. Available in PDF, EPUB and Kindle. Book excerpt:
